`timescale 1ns/1ns
module tb_cpu_top();
reg sys_clk;
reg sys_rst_n;
wire [15:0] test_ip;
wire [15:0] test_instruct;

wire [15:0] inner_reg0;
wire [15:0] reg_da;
wire [15:0] test_data_bus;
wire [15:0] test_data_inner;
wire [9:0] cnt;
wire busy_flag;
wire work_ok;
wire [5:0] state;
wire [15:0] ram_data_buf;

assign inner_reg0 = cpu_top_inst.ctrl_center_inst.inner_reg[0];
assign reg_da = cpu_top_inst.ctrl_center_inst.rw_reg_inst.reg_00.data_reg;
assign test_data_bus = cpu_top_inst.ctrl_center_inst.data_bus;
assign test_data_inner = cpu_top_inst.ctrl_center_inst.rw_reg_inst.reg_00.data_sig_inner;
assign cnt = cpu_top_inst.ctrl_center_inst.instruct_unit_inst.sdal_inst.cnt;
assign busy_flag = cpu_top_inst.ctrl_center_inst.instruct_unit_inst.sdal_inst.busy_flag;
assign work_ok = cpu_top_inst.ctrl_center_inst.work_ok;
assign state = cpu_top_inst.ctrl_center_inst.instruct_unit_inst.sdal_inst.state;
assign ram_data_buf = cpu_top_inst.ctrl_center_inst.rw_ram_inst.data_buf;

initial
begin
	sys_clk <= 1'b1;
	sys_rst_n <= 1'b0;
#60
	sys_rst_n <= 1'b1;
end

always #10 sys_clk = ~sys_clk;

cpu_top cpu_top_inst
(
	.sys_clk(sys_clk),
	.sys_rst_n(sys_rst_n),
	.test_ip(test_ip),
	.test_instruct(test_instruct)
);

endmodule